The present application relates to semiconductor devices, and more particularly to fin field effect transistors (FinFETs) having fully alloyed source/drain regions to reduce on-resistance (Ron) in embedded dynamic random access memory (eDRAM) cells.
A memory cell such as an eDRAM cell comprises a storage capacitor formed in a deep trench in a substrate (i.e., deep trench capacitor) for storing electrical charge that characterizes an information content of the memory cell, an access transistor such as a FinFET formed on top of the substrate and adjacent the deep trench capacitor for addressing the storage capacitor, and a conductive strap structure providing an electrical connection between the deep trench capacitor and the FinFET. Many of these embedded memory cells can be arranged on a single chip or within a single package to define an array.
In FinFETs, high conductivity epitaxial raised source/drain regions formed by selective epitaxy have been commonly used to reduce on-resistance (Ron) in order to obtain a high on-current (Ion). Since the conductive strap structure is normally composed of a conductive semiconductor material such as doped polysilicon, and during selective epitaxy in the formation of source/drain regions, the epitaxial growth of a semiconductor material occurs on the surface of the conductive strap structure as well. As the density of eDRAM cells increases, the epitaxial grown semiconductor materiel may merge semiconductor fins of different transistors or may merge an adjacent semiconductor fin and a conductive strap structure, causing unwanted shorts between neighboring transistors and/or neighboring transistors and deep trench capacitors. As such, there remains a need to avoid electrical shorts between neighboring transistors and/or neighboring transistors and deep trench capacitors.